1. Technical Field
This invention relates in general to electronic circuits and, more specifically, to systems and methods for aligning (i.e., deskewing) signals output by electronic circuits. The invention is particularly applicable to aligning test signal outputs of massively parallel testers for use by semiconductor devices under test.
2. State of the Art
As shown in FIG. 1, a massively parallel tester 10 of the related art is used to test a xe2x80x9cmassivexe2x80x9d number of semiconductor devices 12, each temporarily attached to one of a series of Device Under Test (DUT) boards 14 that connect to the tester 10 via connectors 16 (not all shown). It will be understood that relatively few devices 12 are actually illustrated in FIG. 1 while, in fact, the tester 10 typically tests thousands of devices 12 at once.
The tester 10 sends various test signals to the devices 12 while they are under test. For example, if the devices 12 are Dynamic Random Access Memory (DRAM) devices, the tester 10 typically sends control signals (e.g., RAS, CAS, WE, etc.), address signals, and data signals to each of the devices 12. Unfortunately, skew is typically introduced into these test signals as a result of variations in the driver propagation delay, switching speed, and transmission line effects associated with the different, and often lengthy, paths that these signals take to each of the devices 12. As used herein, xe2x80x9cskewxe2x80x9d means a deviation in the timing relationship among signals that occurs between the location from which the signals are sent and the location at which the signals are received.
Accordingly, a number of methods are used to deskew these signals before they arrive at the devices 12. In one such method, the test signals are observed manually using an oscilloscope, and the timing of the signals is then adjusted to eliminate any skew. While this method works to limit or eliminate skew under the conditions present at the time the deskewing operation takes place, it does not work over time when variations in the tester 10 and its environment vary the skew. In addition, the manual use of an oscilloscope is a cumbersome operation that leads to less than frequent deskewing operations. In another typical method, Time Domain Response (TDR) test equipment sends pulses down the paths normally followed by the test signals in order to determine the delay associated with each path. With this delay determined for each path, the timing of the test signals can be varied so the signals are deskewed upon arrival at their respective device 12. While this method is more convenient than the oscilloscope method described above, the TDR electronics are generally complex and costly.
Therefore, there is a need in the art for an improved system and method for deskewing test and other signals output by a massively parallel tester and other electronic devices that avoid the problems associated with the conventional deskewing methods and devices described above.
In an inventive method for aligning signals (e.g., test signals), the signals are delayed by, for example, delay elements controlled by control circuitry. The delayed signals are then latched in to, for example, DQ flip-flops using a reference clock. The delaying of the signals is then varied until a transition occurs in each of the latched-in delayed signals. At this point, it is possible to align the signals with their rising edges and/or falling edges occurring at the same time by delaying the signals until they transition.
In another embodiment of this invention, the acts of the embodiment described above are followed by adjusting (e.g., delaying) the timing of the latching-in of the delayed signals by a fixed amount of time (e.g., 15 nanoseconds). Once this is accomplished, the delaying of the signals is varied again until a transition occurs in each of the latched-in delayed signals. Then, the delay of each of the signals at which a transition occurs prior to adjusting the timing of the latching-in, the delay of each of the signals at which a transition occurs after adjusting the timing of the latching-in, and the fixed amount of time by which the timing of the latching-in is adjusted are used to characterize a delay function of each of the signals. The delaying of each of the signals is then adjusted in accordance with its respective delay function to align the signals.
In a further embodiment of this invention, circuitry for aligning (i.e., deskewing) a plurality of signals includes circuitry for delaying the signals and circuitry for latching-in the delayed signals. In order to align the signals, control circuitry adjusts the delaying of the signals until a transition occurs in each of the latched-in delayed signals.
In other embodiments of this invention, the circuitry described above is incorporated into a massively parallel test system, a Device Under Test (DUT) board, an interface board, a massively parallel tester, and a semiconductor substrate (e.g., a semiconductor wafer).